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issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. b 05/10/06 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services descri bed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. is63wv1024bll is64wv1024bll 128k x 8 high-speed cmos static ram features ? high-speed access time: 12 ns: 3.3v + 10% 15 ns: 2.5v ? 3.6v ? high-performance, low-power cmos process ? cmos low power operation 50 mw (typical) operating current 25 w (typical) standby current ? multiple center power and ground pins for greater noise immunity ? easy memory expansion with ce and oe options ? ce power-down ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? packages available: ? 32-pin tsop (type ii) ? 32-pin stsop (type i) ? 48-ball minibga (6mm x 8mm) ? 32-pin 300-mil soj ? lead-free available description the issi is63/64wv1024bll is a very high-speed, low power, 131,072-word by 8-bit cmos static ram. the is63/64wv1024bll is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 25 w (typical) with cmos input levels. the is63/64wv1024bll operates from a single v dd power supply. the is63/64wv1024bll is available in 32-pin tsop (type ii), 32-pin stsop (type i), 48-ball minibga (6mm x 8mm), and 32-pin soj (300-mil) packages. functional block diagram a0-a16 ce oe we 128k x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 may 2006
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll pin descriptions a0-a16 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 bidirectional ports v dd power gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 ce i/o0 i/o1 vdd gnd i/o2 i/o3 we a4 a5 a6 a7 a16 a15 a14 a13 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a12 a11 a10 a9 a8 pin configuration 32-pin tsop (type ii) (t) 32-pin stsop (type i) (h) pin configuration 48-mini bga (b) (6 mm x 8 mm) pin configuration 32-pin soj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 ce i/o0 i/o1 vdd gnd i/o2 i/o3 we a4 a5 a6 a7 a16 a15 a14 a13 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a12 a11 a10 a9 a8 1 2 3 4 5 6 a b c d e f g h nc oe a2 a6 a7 nc i/o 1 nc a1 a5 ce i/o 8 i/o 2 nc a0 a4 nc i/o 7 gnd nc nc a3 nc v dd v dd nc nc nc nc gnd i/o 3 nc a14 a11 i/o 5 i/o 6 i/o 4 nc a15 a12 we a8 nc a10 a16 a13 a9 nc
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll truth table mode we we we we we ce ce ce ce ce oe oe oe oe oe i/o operation v dd current not selected x h x high-z i sb 1 , i sb 2 (power-down) output disabled h l h high-z i cc 1 , i cc 2 read h l l d out i cc 1 , i cc 2 write l l x d in i cc 1 , i cc 2 operating range (v dd ) range ambient temperature v dd (15 ns) v dd (12 ns) commercial 0c to +70c 2.5v-3.6v 3.3v + 10% industrial ?40c to +85c 2.5v-3.6v 3.3v + 10% automotive ?40c to +125c 2.5v-3.6v 3.3v + 10% absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.5 to v dd +0.5 v t stg storage temperature ?65 to +150 c p t power dissipation 1.5 w v dd v dd related to gnd -0.2 to +3. 9 v note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll dc electrical characteristics (over operating range) v dd = 2.5v-3.6v symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?1.0 ma 2.3 ? v v ol output low voltage v dd = min., i ol = 1.0 ma ? 0.4 v v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?2 2 a i lo output leakage gnd v out v dd , outputs disabled ?2 2 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width - 2.0 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width - 2.0 ns). not 100% tested. dc electrical characteristics (over operating range) v dd = 3.3v + 10% symbol parameter test conditions min. max. unit v oh output high voltage v dd = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v dd = min., i ol = 8.0 ma ? 0.4 v v ih input high voltage 2 v dd + 0.3 v v il input low voltage (1) ?0.3 0.8 v i li input leakage gnd v in v dd ?2 2 a i lo output leakage gnd v out v dd , outputs disabled ?2 2 a note: 1. v il (min.) = ?0.3v dc; v il (min.) = ?2.0v ac (pulse width - 2.0 ns). not 100% tested. v ih (max.) = v dd + 0.3v dc; v ih (max.) = v dd + 2.0v ac (pulse width - 2.0 ns). not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll capacitance (1) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf note: 1. tested initially and after any design or process changes that may affect these parameters. power supply characteristics (1) (over operating range) -12 ns -15 ns symbol parameter test conditions options min. max. min. max. unit i cc v dd dynamic operating v dd = max., com . ?35 ?30 ma supply current i out = 0 ma, f = f max ind . ?45 ?40 auto ?60 ?50 typ. (2) ?20 ?20 i cc 1 operating supply v dd = max., com . ?5 ?5 ma current iout = 0ma, f = 0 ind . ?5 ?5 auto ?5 ?5 i sb 1 ttl standby current v dd = max., com . ?3 ?3 ma (ttl inputs) v in = v ih or v il ind . ?4 ?4 ce v ih , f = 0 auto ?4 ?4 i sb 2 cmos standby v dd = max., com . ?20 ?20 ua current (cmos inputs) ce v dd ? 0.2v, ind . ?50 ?50 v in v dd ? 0.2v, or auto ?75 ?75 v in 0.2v, f = 0 typ. (2) ?6 ?6 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd =2.5v, t a =25 o c. not 100% tested.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll ac test conditions parameter unit unit (2.5v-3.6v) (3.3v + 10%) input pulse level 0v to v dd v 0v to v dd v input rise and fall times 1.5ns 1.5ns input and output timing v dd /2 v dd /2 + 0.05 and reference level (v ref ) output load see figures 1a and 1b see figures 1a and 1b ac test loads figure 1a. figure 1b. 30 pf including jig and scope zo=50 output v ref 50 319 5 pf including jig and scope 353 output 2.5v
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll read cycle switching characteristics (1) (over operating range) -12 ns -15 ns symbol parameter min. max. min. max. unit t rc read cycle time 12 ? 15 ? ns t aa address access time ? 12 ? 15 ns t oha output hold time 3 ? 3 ? ns t ace ce access time ? 12 ? 15 ns t doe oe access time ? 6 ? 7 ns t lzoe (2) oe to low-z output 0 ? 0 ? ns t hzoe (2) oe to high-z output 0 6 0 6 ns t lzce (2) ce to low-z output 3 ? 3 ? ns t hzce (2) ce to high-z output 0 6 0 6 ns t pu ce to power up time 0 ? 0 ? ns t pd ce to power down time ? 12 ? 15 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.25v, input pulse levels of 0.4v to v dd -0.3v and output loading specified in figure 1. 2. tested with the loading specified in figure 1. transition is measured 500 mv from steady-state voltage. not 100% tested.
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll data valid read1.eps previous data valid t aa t oha t oha t rc d out address t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce = v il . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll write cycle switching characteristics (1,3) (over operating range) -12 ns -15 ns symbol p arameter min. max. min. max. unit t wc write cycle time 12 ? 15 ? ns t sce ce to write end 9 ?10? ns t aw address setup time to 9 ?10? ns write end t ha address hold from 0 ? 0 ? ns write end t sa address setup time 0 ? 0 ? ns t pwe 1 (1) we pulse width ( oe high) 9 ?10? ns t pwe 2 (2) we pulse width ( oe low) 11 ? 12 ? ns t sd data setup to write end 9 ? 9 ?ns t hd data hold from write end 0 ? 0 ? ns t hzwe (2) we low to high-z output ? 6 ? 7 ns t lzwe (2) we high to low-z output 3 ? 3 ? ns notes: 1. test conditions assume signal transition times of 3ns or less, timing reference levels of 1.25v, input pulse levels of 0.4v t o v dd -0.3v and output loading specified in figure 1a. 2. tested with the loading specified in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling ed ge of the signal that terminates the write. ac waveforms write cycle no. 1 (1,2 ( ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll ac waveforms write cycle no. 2 (1) ( we controlled, oe = high during write cycle) write cycle no. 3 ( we controlled: oe is low during write cycle) notes: 1. the internal write time is defined by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falli ng edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe > v ih . data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll data retention waveform ( ce controlled) data retention switching characteristics symbol p arameter test condition operations min. typ. (1) max. unit v dr v dd for data retention see data retention waveform 1.8 ? 3.6 v i dr data retention current v dd = 1.8v, ce v dd ? 0.2v com . ?6 20 a ind . ?6 50 auto .? 6 75 t sdr data retention setup time see data retention waveform 0 ? ? ns t rdr recovery time see data retention waveform t rc ?? ns note : 1. typical values are measured at v dd = 2.5v, t a = 25 o c. not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 05/10/06 issi ? is63wv1024bll is64wv1024bll ordering information industrial range: ?40c to +85c speed (ns) order part no. package 12 is63wv1024bll-12ti 32-pin tsop (type ii) is63wv1024bll-12tli 32-pin tsop (type ii), lead-free is63wv1024bll-12hi stsop (type i) (8mm x13.4mm) is63wv1024bll-12hli stsop (type i) (8mm x13.4mm), lead-free is63wv1024bll-12ji 32-pin soj (300-mil) is63wv1024bll-12jli 32-pin soj (300-mil), lead-free is63wv1024b ll-12bi mbga(6mmx8mm) is63wv1024bll-12bli mbga(6mmx8mm), lead-free automotive range (a3): ?40c to +85c speed (ns) order part no. package 15 (12*) is64wv1024bll-15ta3 32-pin tsop (type ii) is64wv1024bll-15tla3 32-pin tsop (type ii), lead-free is64wv1024bll-15ha3 stsop (type i) (8mm x13.4mm) is64wv1024bll-15hla3 stsop (type i) (8mm x13.4mm), lead-free is64wv1024bll-15ba3 mbga(6mmx8mm) IS64WV1024BLL-15BLA3 mbga(6mmx8mm), lead-free note: 1. speed = 12ns for v dd = 3.3v + 10%. speed = 15ns for v dd = 2.5v-3.6v.
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/25/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 300-mil plastic soj package code: j notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. millimeters inches sym. min. typ. max. min. typ. max. n0. leads 24/26 a 3.56 0.140 a1 0.64 0.025 a2 2.41 2.67 0.095 0.105 b 0.41 0.51 0.016 0.020 b 0.66 0.81 0.026 0.032 c 0.20 0.25 0.008 0.010 d 17.02 17.27 0.670 0.680 e 8.26 8.76 0.325 0.345 e1 7.49 7.75 0.295 0.305 e2 6.27 7.29 0.247 0.287 e 1.27 bsc 0.050 bsc seating plane 1 n e1 d e2 e b e a1 a b c a2
packaging information issi ? 2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/25/03 millimeters inches sym. min. typ. max. min. typ. max. n0. leads 28 a 3.56 0.140 a1 0.64 0.025 a2 2.41 2.67 0.095 0.105 b 0.41 0.51 0.016 0.020 b 0.66 0.81 0.026 0.032 c 0.20 0.25 0.008 0.010 d 18.29 18.54 0.720 0.730 e 8.26 8.76 0.325 0.345 e1 7.49 7.75 0.295 0.305 e2 6.27 7.29 0.247 0.287 e 1.27 bsc 0.050 bsc millimeters inches sym. min. typ. max. min. typ. max. n0. leads 32 a 3.56 0.140 a1 0.64 0.025 a2 2.41 2.67 0.095 0.105 b 0.41 0.51 0.016 0.020 b 0.66 0.81 0.026 0.032 c 0.20 0.25 0.008 0.010 d 20.83 21.08 0.820 0.830 e 8.26 8.76 0.325 0.345 e1 7.49 7.75 0.295 0.305 e2 6.27 7.29 0.247 0.287 e 1.27 bsc 0.050 bsc 300-mil plastic soj package code: j
integrated silicon solution, inc. packaging information issi ? plastic stsop - 32 pins package code: h (type i) notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d1 and e do not include mold flash protru- sions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic stsop (h - type i) millimeters inches symbol min max min max ref. std. n 32 a ? 1.25 ? 0.049 a1 0.05 ? 0.002 ? a2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.007 0.009 c 0.14 0.16 0.0055 0.0063 d 13.20 13.60 0.520 0.535 d1 11.70 11.90 0.461 0.469 e 7.90 8.10 0.311 0.319 e 0.50 bsc 0.020 bsc l 0.30 0.70 0.012 0.028 s 0.28 typ. 0.011 typ. 0 5 0 5 pk13197h32 rev. b 04/21/03 d1 seating plane c d 1 n e s b a1 a a2 e l
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 01/15/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. mini ball grid array package code: b (48-pin) notes: 1. controlling dimensions are in millimeters. mbga - 6mm x 8mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 48 a 1.20 0.047 a1 0.24 0.30 0.009 0.012 a2 0.60 0.024 d 7.90 8.10 0.311 0.319 d1 5.25 bsc 0.207 bsc e 5.90 6.10 0.232 0.240 e1 3.75 bsc 0.148 bsc e 0.75 bsc 0.030 bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 8mm x 10mm millimeter inches sym. min. typ. max. min. typ. max. n0. leads 48 a 1.20 0.047 a1 0.24 0.30 0.009 0.012 a2 0.60 0.024 d 9.90 10.10 0.390 0.398 d1 5.25 bsc 0.207 bsc e 7.90 8.10 0.311 0.319 e1 3.75 bsc 0.148 bsc e 0.75 bsc 0.030 bsc b 0.30 0.35 0.40 0.012 0.014 0.016 seating plane a a1 a2 a b c d e f g h e e d1 e1 e d b (48x) top view bottom view 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. f 06/18/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd . notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref 0.037 ref 0.81 ref 0.032 ref 0.88 ref 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5

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